The present invention relates to a digital signal processor suited for LSI fabrication.
In digital signal processing such as digital filtering and fast discrete Fourier transformation (FFT), the fundamental constituents are multipliers, adder-subtractors and delay elements. These three types of elements are combined to realize desired functions. When digital signal processing technology is applied to the field of communications, real time processing is required.
Digital signal processing circuitry for handling real time processes require high processing speeds, and in the conventional system, hardware has been constructed by employment of independent integrated circuits (ICs), as disclosed in an article entitled "Special-Purpose Hardware for Digital Filtering", by S. K. Freeny, PROCEEDING OF THE IEEE, VOL 63, No. 4, April 1975, PP. 633-648, particularly FIG. 16 on page 643. Such circuitry disadvantageously has a large amount of hardware, since many IC chips including multipliers, adders, random access memories (RAMs) and controllers were used. Particularly, when the operational speed of the multiplier is slower than that required, many multipliers must be used to perform multiplication, resulting in a large scale hardware implementation.
On the other hand, real time digital signal processing circuitry by employment of commercially-available microprocessors has also been contemplated. In this case, bit-slice microprocessors of the bipolar type are much advantageous in arithmetic processing capabilities as compared with microprocessors realized with metal oxide semiconductor (MOS) devices. The most distinctive advantage in using microprocessors over using independent ICs is that identical hardware may be used to achieve many functional operations only by changing the contents of the program memory. However, even with the bipolar bit-slice microprocessor, real time processing for a large amount of computations per unit time cannot be effected at sufficiently high speeds, and eventually a further large scale hardware is required relative to the arrangement by use of independent ICs as mentioned above.
In view of the aforementioned situation, the most advanced device technologies are applied to the development of large-scale integration (LSI) devices for processing digital signals for the purpose of reducing hardware scale, as disclosed in a publication entitled "Multiplier-Accumulator Application Notes", by L. Shirm IV, Trw LSI Products, January 1980, pp. 7-9, particularly FIG. 8, FIG. 11 and FIG. 13. The following four approach directions in developing such LSI devices are considered.
Firstly, reduction in the scale of overall hardware is contemplated by improving the processing speed of independent integrated circuits such as multipliers and adders. In this method, however, reduction of hardware is limited, since each constituent element is separately integrated into an IC chip, and a total power consumption increases because of a high clock rate.
Secondary, a number of multipliers and adders are contemplated to integrate into a single IC chip. In this method, however, individual multipliers and adders must be able to operate independently so as to provide general-purpose capabilities, resulting in a large number of input/output pins and also a requirement of external ICs for timing individual I/O data.
Thirdly, LSIs for exclusive uses are developed at the sacrifice of general-purpose capabilities in order to compensate the drawback in the second method. Large scale integration includes delay elements in addition to the arithmetically operating portions. This method permits the incorporation of large scale integration for specific functions within an accommodation range which can be achieved by the present-day device technologies, providing the best solution for minimizing the scale of hardware for individual circuitry. However, for constructing a system, a variety of LSIs must be designed in small production rate, resulting in an immense manufacturing cost.
Fourthly, signal processors which are the enhancement of microprocessors are developed. In signal processors for implementing real time signals, program read only memories (ROMs), coefficient ROMs, data storage random access memories (RAMs), and multipliers are accommodated in one chip in addition to the arithmetic unit. This method provides versatility in function by way of changing the program. However, since the arithmetic word length is fixed, LSIs with a large word length need to be developed for systems requiring a high computational accuracy. This causes an increase in hardware, resulting in a low processing speed and increased peripheral circuitry. This method is suitable for single channel processing, however, for multi-channel processing, time for data input/output is no longer negligible relative to time for computing and thus processing speed is lowered.
The first method may be put into practice independently or in combination with any of the second, third and fourth methods. As described above, many attempts have been made to realize large-scale integration for real time digital signal processors, and each method has respective advantages and disadvantages. Particularly, LSI devices for multi-channel processing must meet the following conditions:
(1) The device functions must be oriented to general-purpose capabilities.
(2) The number of input/output pins must be as small as possible.
(3) The number of external circuits required must be as small as possible.
(4)The devices must be easy to use for the user.
The above-mentioned conditions are inconsistent with each other. For example, it is generally considered that condition (1) is inconsistent with conditions (2) and (3). Condition (1) weighs with the second of the foregoing methods of large-scale integration, and conditions (2) and (3) weigh with the third method. That is to say, prior art methods of large-scale integration do not satisfy all of conditions (1) through (4) at the same time.